CURPIPE=others, ISEL=0, REW=0, BIGEND=0, RCNT=0, MBW=00
CFIFO Port Select Register
| CURPIPE | FIFO Port Access Pipe Specification 0 (0000): DCP 0 (others): Setting prohibited 1 (0001): PIPE1 2 (0010): PIPE2 3 (0011): PIPE3 4 (0100): PIPE4 5 (0101): PIPE5 6 (0110): PIPE6 7 (0111): PIPE7 8 (1000): PIPE8 9 (1001): PIPE9 |
| ISEL | FIFO Port Access Direction when DCP is Selected 0 (0): Select reading from the FIFO buffer 1 (1): Select writing to the FIFO buffer. |
| BIGEND | FIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| MBW | CFIFO Port Access Bit Width 0 (00): 8-bit width 1 (01): 16-bit width 2 (10): 32-bit width 3 (11): Setting prohibited |
| REW | Buffer Pointer Rewind 0 (0): Do not rewind buffer pointer (Writing 0 has no effect.) 1 (1): Rewind buffer pointer. |
| RCNT | Read Count Mode 0 (0): Clear DTLN[11:0] flags in the FIFO port control register to 000h when all receive data is read from CFIFO 1 (1): Decrement DTLN[11:0] flags each time receive data is read from CFIFO. |